Efficient Protocol Design Flow for Embedded Systems

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Efficient Protocol Design Flow for Embedded Systems
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  Efficient Protocol Design Flow for Embedded Systems Von der Fakult¨at f¨ur Mathematik, Naturwissenschaften und Informatikder Brandenburgischen Technischen Universit¨at Cottbuszur Erlangung des akademischen Grades Doktor der Ingenieurwissenschaften (Dr.-Ing.)genehmigte Dissertationvorgelegt von Dipl.-Inf. Daniel Dietterle geboren am 10. Februar 1978 in Eberswalde-FinowGutachter: Prof. Dr.-Ing. Rolf KraemerGutachter: Prof. Dr.-Ing. J¨org NolteGutachter: Prof. Dr.-Ing. Adam WoliszTag der m¨undlichen Pr¨ufung: 25. Februar 2009  ii  Abstract It is predicted that, in the next years, wireless sensor networks could be massivelydeployed in a wide variety of application areas, such as agriculture, logistics, au-tomation, or infrastructure monitoring. An extremely low power consumption,high dependability, and low cost are common requirements for sensor nodes in allthese applications. This can be achieved only by tiny, power-efficient microcon-trollers and communication systems integrated on a single chip.Formal description techniques, such as SDL (Specification and Description Lan-guage), are suitable to formally prove properties of models designed in these lan-guages. Code generators facilitate the automatic transformation of SDL modelsinto software implementations, while preserving the properties of the model and,thus, achieving high system dependability. The implementations consist of thetranslated state machine behavior and, additionally, require a run-time environ-ment for model execution.The objective of this work was to investigate an integrated design flow forembedded systems, which should allow the development of efficient and dependablesystem implementations from abstract SDL specifications. In this thesis, conceptsfor minimal SDL run-time environment have been devised and realized by anexample implementation.Not only pure software implementations should be considered, but startingfrom these also the hardware/software (HW/SW) partitioning of the system shouldbe supported. For this purpose, a cosimulation framework that allows the couplingof an instruction set simulator (ISS) with a functional SDL simulation has beeninvestigated and prototypically implemented within the scope of this thesis.By shifting functionality to dedicated hardware components it is possible totake computational load from the microcontroller and to decrease the overall en-ergy consumption by reducing the clock frequency and lowering the supply voltage.Due to the use of SDL, the design flow lends itself particularly to the implementa-tion of communication protocols, and is limited to applications with soft real-timerequirements.For an SDL-based design flow targeted to resource-constrained embedded sys-tems, concepts and real implementations of minimal SDL run-time environmentswere lacking. Available software tools, indeed, enable the transformation of SDLmodels into C code, however for an efficient implementation, an integration intoexisting real-time operating systems (RTOS) for small microcontrollers is essential.iii  A prototypical implementation of a run-time library for the Reflex RTOS hasbeen created to validate our general concepts. It is about 30 % faster and con-sumes less than half of the program memory compared to the operating systemindependent run-time environment of the tool vendor Telelogic. For simple SDLmodels, the application requires in total less than 8 kbytes program memory and1 kbyte RAM.For the evaluation of design alternatives that realize different hardware/softwarepartitionings, instruction set simulators are particularly suitable. They facilitatethe identification of performance bottlenecks of the HW/SW system.Test stimuli are required in order to measure the performance and responsetime of systems under design. The development of an environment that generatessuch test signals can be a laborious task. Thus, it is reasonable, especially inthe design of protocols, to use an SDL simulation of a communication network togenerate these test stimuli. Such an SDL model already exists and is the basisfor the implementation. The protocol implementation simulated by the ISS thenbecomes part of the network simulation. An efficient coupling of SDL simulationswith instruction set simulators had to be investigated, and a solution is presentedin this thesis.Based on the general concepts, a cosimulation framework for the ISS TSIM forthe LEON2 processor was realized by the author. The joint SDL and instructionset simulation is very fast, which could be demonstrated by connecting a softwareimplementation of the complex IEEE 802.15.3 medium access control (MAC) pro-tocol with an SDL simulation of a network consisting of four devices. The realexecution time for 10 seconds of simulation time amounted to just 50 seconds.The overall design flow was validated by means of a HW/SW implementationof the IEEE 802.15.3 wireless MAC protocol. The author designed a completeSDL model of the protocol and integrated it into Reflex. By using our cosimulationenvironment for the TSIM simulator, the model was partitioned into hardware andsoftware. For the hardware part, a dedicated protocol accelerator was designed bythe author. This hardware component was integrated on a single chip with theLEON2 processor and, finally, manufactured.It could be shown that the presented methodology enables the design andimplementation of efficient HW/SW systems. Consequently, it can be applied tothe development of dependable and energy-efficient wireless sensor nodes and otherembedded systems. Keywords:  Model-based design, protocol engineering, cosimulation, IEEE802.15.3.iv
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